1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to interconnect structures for signal exchange in complex integrated circuits.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation, to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors, interconnect structures and the like, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
Although, in highly complex integrated circuits, transistor elements are the dominant circuit element which substantially determine the overall performance of these devices, other components, such as capacitors and resistors and, in particular, a complex interconnect system or metallization system, may be required, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area.
Typically, as the number of circuit elements, such as transistors and the like, per unit area may increase in the device level of a corresponding semiconductor device, the number of electrical connections associated with the circuit elements in the device level may also be increased, typically even in an over-proportional manner, thereby requiring complex interconnect structures which may be provided in the form of metallization systems including a plurality of stacked metallization layers. In these metallization layers, metal lines, providing the inner level electrical connection, and vias, providing intra level connections, may be formed on the basis of highly conductive metals, such as copper and the like, in combination with appropriate dielectric materials, so as to reduce the parasitic RC (resistive capacitive) time constants, since, in sophisticated semiconductor devices, typically, signal propagation delay may be substantially restricted by the metallization system rather than the transistor elements in the device level. However, expanding the metallization system in the height dimension so as to provide the desired density of interconnect structures may be restricted by the parasitic RC time constants, the limitations imposed by the material characteristics of sophisticated low-k dielectrics and the heat dissipation capability. That is, typically, a reduced dielectric constant is associated with reduced mechanical stability of these dielectric materials, thereby also restricting the number of metallization layers that may be stacked on top of each other in view of yield losses during the various fabrication steps and the reduced reliability during operation of the semiconductor device. Moreover, the increasing current density in the metal line, in combination with increased waste heat produced in the device level, may require a superior heat conductivity, which may not be compatible with a high packing density of metal lines and a reduced dielectric constant of the dielectric materials of the metallization system.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.